A flash memory device is a non-volatile memory that does not require power such as a battery backup to retain its memory contents. Conventional flash memory devices store charge on a floating gate to represent one of the two binary states, such that lack of stored charge represents the other binary state. A typical flash memory device is configured to perform three basic operations as follows: a read operation, a write operation, and a block erase operation.
Unlike other conventional forms of memory and mass storage, the amount of time necessary to write (program) a bit and also to erase is substantial. Further, a bit cannot simply be changed. The state of a programmed bit must be erased and then reprogrammed. Nevertheless, flash memory is being used as a substitute for rotating magnetic media in computers. With conventional rotating magnetic media as a data or program file is altered simply by rewriting the data. Because of the necessity of an erase before write, data is handled differently on a flash memory.
Flash memory for mass storage is typically arranged in blocks. Each block includes a plurality of addressable sectors, each having a logical block address LBA. In a conventional system, if the data or program stored within a block is to be changed, the data in that source block is first read out of the flash memory and stored in a buffer latch. An erased block in the same flash device is identified as a destination block. Those sectors that are to remain unchanged are then programmed into the corresponding LBAs of the destination block, and the changed data is programmed into the remaining LBAs of the destination block.
Conventional flash memory devices first transfer the data to be moved from the source block (inside the flash array) onto a flash data latch. Subsequently, a controller reads the data stored on the flash of data latch one byte (eight bits) at a time and then sequentially stores each byte of this data onto an external memory device. The flash memory must transmit its data sequentially because it cannot have unlimited input/output pins. Eight bits is exemplary; a flash memory could be constructed with a different number of data input/output pins. Next, the controller sequentially writes each byte of this data that is stored on the external memory device back onto the flash data latch. Finally, the controller issues a program command that writes the data within the plurality of data latches onto the destination block inside the flash array. In conventional flash memory devices, this step of sequentially shifting out the data from the flash data latch onto the external buffer is a time-consuming step. Likewise, this step of sequentially shifting the data from the external memory device back onto the flash data latch is also time-consuming. These mentioned time-consuming steps of sequentially shifting data in and out of the flash memory device degrade the performance of the device.
For example, FIG. 1 illustrates a typical flash memory device 100. A flash array 105 contains electronic circuits which is configured to store the data. A command/control logic 130, an address latch 150, a latch decoder 140, a 528 byte latch 110, a plurality of input/output buffer latches 120, an input/output data bus 145, and an external controller 135 are coupled to the flash array 105. The command/control logic 130 coordinates the timing between the address latch 150, the 528 byte latch 110, the input/output buffer latches 120, and the flash array 105.
In use, when a plurality of predetermined sectors within the flash array 100 are to be transferred to a different block within the same flash array 105, the command/control logic 130 reads the data from the flash memory 105 to the latch 110, and controller 135 sequentially transfers the data from the latch 110 to the external controller 135 into a data buffer 141. After each of the plurality of sectors is read into the data buffer 141, the external controller 135 then proceeds to sequentially write each of the plurality of sectors onto the 528 byte latch from the data buffer 141. After each of the plurality of sectors is written back onto the 528 byte latch, then the plurality of sectors are transferred to a new location in the flash array 105. The steps of sequentially shifting the data out from the flash array 105 to the external controller 135 and then sequentially shifting the data back to the flash array 105 from the external controller 135 are time consuming and needlessly waste resources of the memory device 100.
FIG. 2 illustrates a timing diagram of the flash memory device 100 (FIG. 1) showing the chip enable, address enable, write enable, read enable, and busy indicators. Reference to FIG. 1 will enhance understanding of FIG. 2 and this description thereof. At time T0 the "read" command is given by the external controller 135 and the flash memory device 100 is initialized by activating the chip enable and write enable functions. Next, at time T1 the "source address" is provided and the address enable input is activated to latch the address and the write enable input is also activated. At this stage, the source address is saved in the address latch 150. The ready indicator is activated between times T0 and T2. Between time T2 and time T3, is a transition period and the busy signal is activated. At this time, the data from the flash array 105 is transferred to the latch 110. At time T3, RDY is asserted to indicate that the data is ready to be shifted out by the external controller 135. At time T3 the data to be rewritten is sequentially read out of the flash memory device 100 and the read enable function is activated for each byte of data that is read. Next, at time T4 the "serial in" command is given, and the flash memory device 100 is initialized by activating the command/latch enable and write enable functions. At time T5 the "destination address" is provided to the flash memory and the address enable and the write enable functions are activated to store the destination address in the address latch 150. Next, at time T6 the data is sequentially written back into the 528 byte latch 110 from the external controller 135. The write enable function is activated for each byte of data that is written to the flash memory device 100. Between time T7 and time T8, the "write" command is given. Immediately following the write command function, the write enable function is activated to simultaneously transfer the data residing in the 528 byte latch 110 into the flash array 105 at the destination address. The busy indicator is activated between time T8 and time T9. After time T9, RDY is activated to indicate the end of write.
What is needed is a flash memory device that is configured to rewrite data from one location within a flash array to another location within the same flash array without sequentially shifting this data out of the flash memory onto an external memory device and then sequentially shifting the same data back into the flash memory. What is further needed is a controller that identifies a free memory block within the same flash memory for multiple flash memory systems.